In the manufacture of semiconductor devices, an important aspect is represented by the possible role of the package of the device.
One of the lines followed in the context of reduction of costs of these devices is hence the reduction in the cost of the package, pursued, for example, through a reduction of the costs of the metal frames (on which the chip is attached) and of the resins inside the package.
Such a saving may have an effect on the thicknesses of the frames and/or on the quality of the resins and may result—in particular in devices of a low-cost type, designed to be used in consumer goods—in effects such as a shift in the output voltage VOUT of the device after assembly.
Such a phenomenon may be amplified by the possible development of stresses, in the sense that it is possible to detect a discrepancy between, for example, the output value VOUT obtained at the level of electrical wafer sorting (EWS) after so-called “trimming” of the device and the values VOUT that can be detected after packaging of the chip.
The above phenomenon may be at least in part attributed to the pressure that the resin exerts on the surface of the chip. This pressure may induce a deformation of the chip, with a consequent distortion of the crystal lattice of the semiconductor material (e.g., silicon), with the effect of distortion, which may be more marked in the presence of frames, with values of thickness that, being smaller than standard values, are exposed to a significant degree of bending.
By way of example, it is possible to encounter values of voltage shift that may range between 3 mV and 5 mV and reach, in some cases, values in the region of 100 mV. Values of shift of +/−3 mV up to +/−12 mV may be found in normal production in the case of large production lots.
The direction of the shift may be unforeseeable, and hence be either positive or negative according to the type of package, with the possibility of encountering for one and the same chip different values of voltage shift—both as regards modulus and direction—according to the package in which the chip is assembled.
In such a context, there is in general felt the need to have available solutions that will enable control of these shifts, there being desirable also a reduction in costs for carrying out tests.
In this perspective, it has been proposed to trim the device after packaging, using, for example, an external pin, without inserting in the chip circuit blocks programmable from outside. This solution, albeit interesting, presents limits in terms of occupation of space and increase in cost of the die so that it can be considered inapplicable to standard production devices.
There is a need in the art to contribute to meeting the need outlined above, overcoming the limits referred to previously.